Forum Discussion
Altera_Forum
Honored Contributor
14 years agoIO buffers
Hi guys i am doing synthesis at module level and IO buffers are being implemented by the tool.. I dont want these buffers to be implemented. Can anybody help me with the constraints for not infe...
Altera_Forum
Honored Contributor
14 years agoYes.
The 2ns IO buffer delay will go away. I also wonder if that long IC delay will go away too. If that FF feeds a lot of I/O that are placed around the die, it will have terrible timing. That being said, you currently have a timing constraint on the I/O for it to be analyzed. I find it difficult to analyze I/O on a sub-module that won't be I/O once it's all hooked together. Your timing depends so much on what it drives and where it's placed, it's really hard to do correctly. I tend to leave that for integration(but try to make sure the connections are as short as possible, i.e. register the outputs)