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Altera_Forum's avatar
Altera_Forum
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15 years ago

Invalid output from MM--> ST (SGDMA)

Hi,

Im wondering if anyone experience this problem before. i was transferring content in my SDRAM to a DCFIFO outside of SOPC using SGDMA. The SDRAM content is all zeros. but after the SGDMA transfer, i can see 1 in the upper bytes, and 0 in the lower bytes as shown in the attached picture.

The FF in the first 2 byte is correct, that is not the problem.

Michael

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    No I haven't faced a problem like that... Are you sure that the RAM contents is 0? Especially if you have a data cache, ensure that it is flushed before you start the transfer.

    Is the DMA reading at the correct address?

    Use a Signaltap instance to monitor what the SGDMA is doing.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The problem was solved.. it turns out to be a "loose" wire between FPGA and acq board that is causing this problem.