Internal LVDS for between-board communicatino

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A simple, well defined protocol with separate bit and sync clock is SPI. At 40 Mbit/s, the clock to data skew is low enough, to guarantee correct alignment without special means (as DPA), even through 10 or 20 m of twisted pair cable. A center aligned sampling is preferable, normally.

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Do you refer to the Serial Peripheral Interface SPI ? Because it doesn't have a separate frame sync signal, AFAIK, only a clock, data and in some cases a chip-select signal.

Or did you mean the SPI-4.2 protocol ?

In any case, are you perhaps aware of any Altera-provided megafunctions that can help me establish a physical-layer protocol relatively easily ?

LVDS is good I/O standard for interchip and also interboard communication to my opinion, I have used it in several system designs, for lower distances with FPGA internal drivers. A reason not to use internal LVDS I/O are mainly requirements of overvoltage protection. Main adavantages are low generated EMI and matched impedance transmission at low power.

The protocol used through this physical channel is another thing. Generally, a synchronous transmission needs a bit clock and a sync signal (or frame clock). In some variants, the bit clock is generated from the frame clock by a a PLL (usually with high speed serial I/O) or bit and sync clock are reconstructed from a special coded data channel (e. g. by 8b/10b coding). Alternatively, you can use asynchronous (UART) transmission.

A simple, well defined protocol with separate bit and sync clock is SPI. At 40 Mbit/s, the clock to data skew is low enough, to guarantee correct alignment without special means (as DPA), even through 10 or 20 m of twisted pair cable. A center aligned sampling is preferable, normally.

Thanks for the tips. My motivation to go for LVDS stems from electrical requirements, and not particularly speed. The two cards' digital grounds are not shorted together, and differential is the best way I can see to transfer data between them.

Therefore, I think I'll still go for LVDS, low speed nonwithstanding (unless there are better options you can suggest). The choice is now between internal Stratix II LVDS and an external RXTX LVDS device.

I'll go for source-synchronous for sure, because there's no way to share a clock between the cards. When using the internal LVDS, is it completely transparent to top level code, i.e. does the corresponding Altera megafunction just present a "data_out" signal, that will come out as differential from 2 pins ?

Also, if my clock speed is 40 MHz, and the transmission rate is also 40 MHz, I guess I"ll must use a DPA at the receiving end to shift the clock by 180 degrees ? Or is it better to multiply ?

If doing something source-synchronous(i.e. sending the clock with the data), you could just invert the clock and have 12.5ns of setup and hold margin. The main thing to be concerned about is your clock, as you want to make sure there is no ringing, glitching, cross-coupling, etc. As long as that's all right, your data should have enough margin that if it does have any problems, they will settle down by the time the actual clock comes along. The only downside of source-synchronous is that the clock domain that comes back with the data will not be in synch with your internal clock, so you need to account for that. At 40MHz, you could just send a clock to both chips and you should be fine.

DPA is definitely not required.

At 40MHz you don't need to worry. However, I don't know if LVDS is the right choice for such a slow clock speed. You could do what you need to with just regular I/O. If it were me, I would run a serial data trace and a clock trace using regular I/O. Then just treat the interface as you would any source-synchronous interface.

Again at 40MHz you've got a lot of flexibiliity but your life will be easier if you've matched the trace lengths between the FPGA and connector on both boards and if your connector is impedance matched to your trace impedance. If you've got one trace that's noticably longer than the others, use this as your clock trace, then you may not need to phase delay your clock within the FPGA.

Jake

The answer to the typical question "how fast and how much long" is not simple. The signal frequency vs. distance issue is strictly cable-dependant, and especially varies with cable size, quality of the shield and quality of the twist for each pair.

But you are speaking of 40MHz, which is realy low speed for LVDS and you should not have any problem with 20cm. At least be sure of a good shielding of your cable and the resulting eye pattern shoul be clean enough for a correct data recovery.