Internal LVDS for between-board communicatino

If doing something source-synchronous(i.e. sending the clock with the data), you could just invert the clock and have 12.5ns of setup and hold margin. The main thing to be concerned about is your clock, as you want to make sure there is no ringing, glitching, cross-coupling, etc. As long as that's all right, your data should have enough margin that if it does have any problems, they will settle down by the time the actual clock comes along. The only downside of source-synchronous is that the clock domain that comes back with the data will not be in synch with your internal clock, so you need to account for that. At 40MHz, you could just send a clock to both chips and you should be fine.