Internal LVDS for between-board communicatino

At 40MHz you don't need to worry. However, I don't know if LVDS is the right choice for such a slow clock speed. You could do what you need to with just regular I/O. If it were me, I would run a serial data trace and a clock trace using regular I/O. Then just treat the interface as you would any source-synchronous interface.

Again at 40MHz you've got a lot of flexibiliity but your life will be easier if you've matched the trace lengths between the FPGA and connector on both boards and if your connector is impedance matched to your trace impedance. If you've got one trace that's noticably longer than the others, use this as your clock trace, then you may not need to phase delay your clock within the FPGA.

Jake