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Honored Contributor
Honored ContributorInternal LVDS for between-board communicatino
Hello, Suppose that I have two boards with Stratix II FPGAs. The boards sit close to each other, and lines from one FPGA reach the other, via a connector. The total length is circa 20 cm (8 inc...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- A simple, well defined protocol with separate bit and sync clock is SPI. At 40 Mbit/s, the clock to data skew is low enough, to guarantee correct alignment without special means (as DPA), even through 10 or 20 m of twisted pair cable. A center aligned sampling is preferable, normally. --- Quote End --- Do you refer to the Serial Peripheral Interface SPI ? Because it doesn't have a separate frame sync signal, AFAIK, only a clock, data and in some cases a chip-select signal. Or did you mean the SPI-4.2 protocol ? In any case, are you perhaps aware of any Altera-provided megafunctions that can help me establish a physical-layer protocol relatively easily ?
