Honored Contributor
Honored ContributorLVDS is good I/O standard for interchip and also interboard communication to my opinion, I have used it in several system designs, for lower distances with FPGA internal drivers. A reason not to use internal LVDS I/O are mainly requirements of overvoltage protection. Main adavantages are low generated EMI and matched impedance transmission at low power.
The protocol used through this physical channel is another thing. Generally, a synchronous transmission needs a bit clock and a sync signal (or frame clock). In some variants, the bit clock is generated from the frame clock by a a PLL (usually with high speed serial I/O) or bit and sync clock are reconstructed from a special coded data channel (e. g. by 8b/10b coding). Alternatively, you can use asynchronous (UART) transmission. A simple, well defined protocol with separate bit and sync clock is SPI. At 40 Mbit/s, the clock to data skew is low enough, to guarantee correct alignment without special means (as DPA), even through 10 or 20 m of twisted pair cable. A center aligned sampling is preferable, normally.
