interface stratixIV with an external ultrafast comparator

Shalom,

Reading back all the previous posts, I do agree Josyb about the following points:

1) You MUST use the GXB RX in “Lock To Reference” mode because your comparator output data being (roughly NRZ) random, there is no guarantee for the CDR unit to be able to properly recover the data (in other words: no embedded clock into the data).

2) You can bypass the PCS (RX PMA only) unless you have several comparators (multiple 1-Bit receivers) that need to be synchronized (in phased array application for instance). In that case, you can either use the word aligner + RX phase comp FIFO of the PCS or use a PMA-only channel with a synchronization state machine implemented in the FPGA fabric.

3) You’d better use an external dedicated clock generator to latch your comparator (Analog Device chip, Maxim, etc…). Stx Transceivers are targeted to high-speed digital data transmission and not clock generation. If your very first requirement is to achieve a low-jitter, do not use a GXB TX as a clock generator even if it’s look like a “charming” solution. Unless you have stringent cost reduction objectives, put an additional low-jitter programmable PLL device on your board.

Now, I have additional remarks:

Concerning the comparator/FPGA interface, I would add a high-speed DFF gate (ONsemi, Hittite, etc…) between the latch comparator and the Stx: In fact, when the Latch Enable input is HIGH, the comparator behaves like a basic analog comparator: it’s output may change accordingly to the random input signal. When LE input is LOW, the comparator stops comparing and hold the status of its output at the instant LE is switched LOW. That means The GXB RX have only a half clock period to properly sample the data. In adding an external DFF, it will have a full clock period to perform its job. When running @10 or 5 GHz, a clock period is short so a half period is very, very short… and I don’t speak about rise/fall times and jitter that reduce your valid time window.

Coupling between comparator/FPGA: the GXB RX need a common mode voltage of 0.82 or 1.1V. The ADCMP output Vcm is 2.2V (@Vcco=2.5V) è You will have to use AC-coupling: is it compatible with your requirements ?… Mind the behavior GXB RX Buffer if your comparator outputs a 000000… or 111111… pattern !

Finally, if you have to process the output of only a single 1-Bit receiver, why do you target a Stx IV device ? To demultiplex the high-speed bit rate, you could implement an external demux device as well (Maxim MAX3950 or Inphi 1385-DX) and process the demultiplexed data in a cheaper and less complex device.