interface stratixIV with an external ultrafast comparator

You should make him think again.

The idea is to keep the receiver in 'lock-to-reference' mode using the ATX PLL generated clock to shift in the data. In the Megawizard you set everything to 'bypass' and you will then get the 'raw' output of the deserialiser into the logic array. From there on starts your work interpreting the sampled data. You can use the Tx and Rx of the GT receivers separately (at least that is what I'm going to do in my Stratix II GX project). So you don't need to use the Tx part to sample your data on the Rx pins. Just make sure that the data is presented with the proper timing. Again you can simulate this with a small Quartus project.