interface stratixIV with an external ultrafast comparator

The GX/GT pins are connected to the GX/GT blocks and I didn't see a possibility to drive them directly from the a PLL or any other logic for that matter. You could ask your FAE to verify that. However generating the clock via the GX/GT block like I described is not difficult nor that time consuming. I normally make a small project to test such things using the Quartus internal simulator in timing mode (in fact that's what I'm doing now for a StratixII GX project ...)