Honored Contributor
Honored Contributorwhat we can tell for the application: we have a periodic random signal that we want to sample.
this random periodic signal can be a high accuracy radar echo that we want to sample. We expect comparator output pulses of 100-200ps width, and larger. Given that the signal is periodic, we can sample at each period at a different phase, by driving the Latch input at different phase! A StratixIV PLL can generate a clock with a 78ps phase delay (dynamically reconfigurable), so we can sample at each period, with this clock , at phase delays of 78ps, so having a sampling rate of 78ps. So what is most important for us now, is to achieve a relatively low jitter, and not necessarily a high speed... Later, we will also want to sample this periodic signal also with the aid of GT receiver megafunction.. but NOW we want to check what are the limit whithout using GT magafunction. This is why we are asking, is there any possibilitys of using GT I/O PIN without using GT megafunction , just to use the high frequency capability of those PIN, if there ? in order that the signal can enter the FPGA with a minimum distortion-from comparator output; or output the FPGA with a minimum jitter, to drive the Latch input.
