Honored Contributor
Honored ContributorLooking at the DC and Switching Characteristics page 1-38 and 1-39 Altera specifies/mentions a 0.32 UI total jitter for the XLAUI/CAUI case and also .032 UI for the SFI-S transmitter at 11.3 Gbps. This comes down to 27.6 ps.
Both specs have high RefClk frequencies (644.53 and 706.25) driven at the dedicated reference clock inputs. Shalom, that's about what I had in mind. However just using the physical IO is not enough, you'll have to pass via the GT blocks, but you can use the MegaWizard to generate the TX-part to generate the Latch signal and the RX-part to sample the incoming signal. To achieve the phased sampling you will probably have to use an external oscillator with a variable phase. I don't see any references in the Stratix IV doc about this. Remember the GX/GT blocks are made for communication and as such only need to generate a 90 degree (or centered) internal clock to sample the incoming data stream. Using an internal PLL to feed the GT block is a possibility but the jitter may be higher?
