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Altera_Forum
Honored Contributor
16 years agointerface DAC in VHDL
Hi,
I´m trying to interface a DAC converter in VHDL with board DSP Development Board for Stratix II Edition, in order to send a pulse, but i´m new in this type of design language. so i need some help. I´m interested in the vhdl code if it would be possible. Thank you very much.10 Replies
- Altera_Forum
Honored Contributor
What kind on dac? Parralel LVDS, SPI, I2C....
- Altera_Forum
Honored Contributor
it's parallel (dac5672 from ti)
- Altera_Forum
Honored Contributor
It's verilog..
module top ( data2dac, clk, clkA, wrtA, mode ); output reg [13:0] data2dacA; input clk; output clkA; output wrtA; output mode; assign mode = 1'b1; assign clkA = clk; assign wrtA = clk; reg [13:0] tmp; always @(posedge clk)begin tmp <= tmp +1'h1; //saw waive. data2dacA <= tmp;// 4 speed end endmodule; - Altera_Forum
Honored Contributor
thank you ARTEM_BOND
i didn't study verilog but i try to understand this code and transform it to vhdl i have just one question what do you mean by this line "assign mode = 1'b1;" ? - Altera_Forum
Honored Contributor
Page 3 "Mode Select: H – Dual Bus, L – Interleaved. Internal pullup.". It's a DAC pin. Select operation mode. If mode = 1'b0 it will not work. - Altera_Forum
Honored Contributor
i know that mode is a dac pin , but i mean what 1'b1 or 1'b0 does mean ? i think it doesn't exist in vhdl
- Altera_Forum
Honored Contributor
mode should be a std_logic output port, then:
mode <= '1'; - Altera_Forum
Honored Contributor
--- Quote Start --- mode should be a std_logic output port, then: mode <= '1'; --- Quote End --- Or you can connect this ping directly to +3.3v. Or leave this pin free. - Altera_Forum
Honored Contributor
ok thank you very much
- Altera_Forum
Honored Contributor
hi. how do i modify your code for AD5620 DAC?