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Altera_Forum's avatar
Altera_Forum
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15 years ago

interface DAC in VHDL

Hi,

I´m trying to interface a DAC converter in VHDL with board DSP Development Board for Stratix II Edition, in order to send a pulse, but i´m new in this type of design language.

so i need some help. I´m interested in the vhdl code if it would be possible. Thank you very much.

10 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    It's verilog..

    module top

    (

    data2dac,

    clk,

    clkA,

    wrtA,

    mode

    );

    output reg [13:0] data2dacA;

    input clk;

    output clkA;

    output wrtA;

    output mode;

    assign mode = 1'b1;

    assign clkA = clk;

    assign wrtA = clk;

    reg [13:0] tmp;

    always @(posedge clk)begin

    tmp <= tmp +1'h1; //saw waive.

    data2dacA <= tmp;// 4 speed

    end

    endmodule;
  • Altera_Forum's avatar
    Altera_Forum
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    thank you ARTEM_BOND

    i didn't study verilog but i try to understand this code and transform it to vhdl

    i have just one question

    what do you mean by this line "assign mode = 1'b1;" ?
  • Altera_Forum's avatar
    Altera_Forum
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    i know that mode is a dac pin , but i mean what 1'b1 or 1'b0 does mean ? i think it doesn't exist in vhdl

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor

    --- Quote Start ---

    mode should be a std_logic output port, then:

    mode <= '1';

    --- Quote End ---

    Or you can connect this ping directly to +3.3v. Or leave this pin free.