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Altera_Forum's avatar
Altera_Forum
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15 years ago

interface DAC in VHDL

Hi, I´m trying to interface a DAC converter in VHDL with board DSP Development Board for Stratix II Edition, in order to send a pulse, but i´m new in this type of design language. so i need som...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

mode should be a std_logic output port, then:

mode <= '1';