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Honored Contributor
Honored Contributorinterface DAC in VHDL
Hi, I´m trying to interface a DAC converter in VHDL with board DSP Development Board for Stratix II Edition, in order to send a pulse, but i´m new in this type of design language. so i need som...
Altera_ForumHonored Contributor
Honored Contributorthank you ARTEM_BOND
i didn't study verilog but i try to understand this code and transform it to vhdl i have just one question what do you mean by this line "assign mode = 1'b1;" ?
