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Altera_Forum's avatar
Altera_Forum
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16 years ago

interface DAC in VHDL

Hi, I´m trying to interface a DAC converter in VHDL with board DSP Development Board for Stratix II Edition, in order to send a pulse, but i´m new in this type of design language. so i need som...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

It's verilog..

module top

(

data2dac,

clk,

clkA,

wrtA,

mode

);

output reg [13:0] data2dacA;

input clk;

output clkA;

output wrtA;

output mode;

assign mode = 1'b1;

assign clkA = clk;

assign wrtA = clk;

reg [13:0] tmp;

always @(posedge clk)begin

tmp <= tmp +1'h1; //saw waive.

data2dacA <= tmp;// 4 speed

end

endmodule;