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ericmtzr's avatar
ericmtzr
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Intel PSG PCIe Cyclone V SX timing question

The customer is using either an Altera Cyclone part or a Critical Link board with Cyclone on it. This question came in from Critical Link regarding PCIe timing. A customer use the MitySOM-5CSX S...
Wincent_Altera's avatar
Wincent_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,


Thanks for make this question more clear.

If refer to latest version of user guide "V-Series Avalon-MM DMA Interface for PCIe Solutions User Guide"

under C. Document Revision History, it mention that


"Mentioned in the Features section that this IP supports the Separate Reference Clock No Spread Spectrum (SRNS) architecture and not the Separate Reference Clock with Independent Spread Spectrum (SRIS) architecture."


Hope this clarified. Regards,

Wincent_Intel