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New Contributorintel_onchip_Memory II RAM: r/w doesn t work from FPGA but from HPS
Hi Guys,
please excuse me, I made such a bad mistake.
I forgot to implement the interface Signal Names to the Soc Implementation.
Now I can read and write to and from the RAM.
// Interne Signale für RAM-Schreiblogik
reg [7:0] ram_addr_reg; // Adresse für On-Chip-RAM (128-Bit Wortadressierung)
reg [127:0] ram_writedata_reg; // Daten für RAM
reg ram_write_reg; // Write Enable für RAM
reg [15:0] ram_byteenable_reg;// Welche Bytes im Wort geschrieben werden
reg ram_writing; // FSM: RAM wird beschrieben
reg [127:0] ram_readdata;
reg ram_read;
wire [7:0] ram_1_s1_address;
wire [127:0] ram_1_s1_writedata;
wire ram_1_s1_write;
wire [15:0] ram_1_s1_byteenable;
wire ram_1_s1_read;
wire [127:0] ram_1_s1_readdata;
// Verbindungen zu Qsys-RAM-Ports
assign ram_1_s1_address = ram_addr_reg;
assign ram_1_s1_writedata = ram_writedata_reg;
assign ram_1_s1_write = ram_write_reg;
assign ram_1_s1_byteenable = ram_byteenable_reg;
assign ram_1_s1_read = ram_read;//1'b0; // nur schreiben
assign ram_1_s1_readdata = ram_readdata;
assign ram_1_s1_clk = fpga_clk_100;
assign ram_1_s1_reset = fpga_reset_n;
assign ram_1_s1_reset_req = 1'b0;Greez, idiot
Super ContributorBased on your description, the issue is likely related to how the FPGA logic is interfacing with the on-chip RAM, specifically with address decoding, byte enables. Since the RAM works correctly when accessed from the HPS (C program), but not from the FPGA, the problem is likely in your RTL or Qsys interconnect configuration.
If only the first or last byte changes, this often points to incorrect byte enable signals or address alignment issues in your FPGA logic.
The fact that the HPS can read/write all bytes correctly suggests the RAM and its initialization are fine, and the Qsys interconnect is functional for the HPS side.
When the FPGA writes, if only one byte is affected, check:
- The width and alignment of your address bus
- The byte enable signals from your FPGA logic to the RAM.
- That you are not inadvertently writing only to address 0 or the highest address due to address calculation errors.
Regards, Richard
LinusGrunHi Richard,
thank you for your answer.
When the FPGA writes, if only one byte is affected, check:
- The width and alignment of your address bus
- The byte enable signals from your FPGA logic to the RAM.
Does anyone have an example for writing and reading Ram from FPGA via Avalon Bus as Master?
With the signals:
- Address
- Byteenable
- Readdata
- Writedata
Thank you for your help.Mit besten Grüßen,
Linus- LinusGrun
Hi Guys,
please excuse me, I made such a bad mistake.
I forgot to implement the interface Signal Names to the Soc Implementation.
Now I can read and write to and from the RAM.
// Interne Signale für RAM-Schreiblogik
reg [7:0] ram_addr_reg; // Adresse für On-Chip-RAM (128-Bit Wortadressierung)
reg [127:0] ram_writedata_reg; // Daten für RAM
reg ram_write_reg; // Write Enable für RAM
reg [15:0] ram_byteenable_reg;// Welche Bytes im Wort geschrieben werden
reg ram_writing; // FSM: RAM wird beschrieben
reg [127:0] ram_readdata;
reg ram_read;
wire [7:0] ram_1_s1_address;
wire [127:0] ram_1_s1_writedata;
wire ram_1_s1_write;
wire [15:0] ram_1_s1_byteenable;
wire ram_1_s1_read;
wire [127:0] ram_1_s1_readdata;
// Verbindungen zu Qsys-RAM-Ports
assign ram_1_s1_address = ram_addr_reg;
assign ram_1_s1_writedata = ram_writedata_reg;
assign ram_1_s1_write = ram_write_reg;
assign ram_1_s1_byteenable = ram_byteenable_reg;
assign ram_1_s1_read = ram_read;//1'b0; // nur schreiben
assign ram_1_s1_readdata = ram_readdata;
assign ram_1_s1_clk = fpga_clk_100;
assign ram_1_s1_reset = fpga_reset_n;
assign ram_1_s1_reset_req = 1'b0;Greez, idiot
