New ContributorIntel FPGA I2C Agent Avalon-MM Host Bridge Core
Hi,
I'm trying to use Intel FPGA I2C Agent Avalon-MM Host Bridge Core to read FPGA's memory content through I2C. But I'm stuck in the first step. I cannot make the IP work.
I included .qsys and .qip files to my project and used the code in page 207 of https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf as my top module. But I couldn't compile the design.
Then I tried to change the top module code as the picture below. I could successfully compile the design and download it to MAX10 Development board. But the IP didn't work. It didn't generate the ACK bit at all. (I tested it experimentally)
Is there any example or application note which explains how to utilize this IP? Do I need to make any changes in the Verilog/VHDL files generated by the IP Parameter Editor?
Here is my configuration for the IP. I tried to make it simple.
I followed Random Address Read operation to read from the FPGA. The Master sends the FPGA address (0x55) with 0 for R/!W bit in the CONTROL BYTE. Then the master sends one address byte (0x50). Since it is on Byte Addressing mode = 1, the master then restarts and sends the CONTROL BYTE with 1 for R/!W bit. In this whole operation, the FPGA does not generate ACK bit.
