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Reza5's avatar
Reza5
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2 years ago

Intel FPGA I2C Agent Avalon-MM Host Bridge Core

Hi, I'm trying to use Intel FPGA I2C Agent Avalon-MM Host Bridge Core to read FPGA's memory content through I2C. But I'm stuck in the first step. I cannot make the IP work. I included .qsys and .q...
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Programmable Logic Device
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
2 years ago

I can't find an example design for this IP.

However the example design below (1. based on SPI and 2. I2C master) could still be a good design reference starter.

1. MAX 10 - SPI Slave to Avalon Master Bridge for MAX10 Dev Kit

https://www.intel.com/content/www/us/en/design-example/715042/max-10-spi-slave-to-avalon-master-bridge-for-max10-dev-kit.html?wapkw=I2C%20Slave%20to%20Avalon-MM%20Master%20bridge%20Core

2. MAX 10 - I2C Remote System Update Example

https://www.intel.com/content/www/us/en/design-example/714746/max-10-i2c-remote-system-update-example.html?wapkw=I2C%20Intel%20FPGA%20ACK%20signal

Best Regards,

Richard Tan

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