Forum Discussion
New ContributorIntel Cyclone 10 LP FPGA DATA0 and DCLK waveforms
Hello,
particularly the DCLK waveform doesn't look acceptable to me, the slow risetime is at risk to cause double clock edges at the receiver.
I guess you are performing PS configuration with open drain drivers, e.g. generated by a x51 processor. You should add pull-up resistors to the DCLK and DATA0 lines, or configure push-pull drivers if possible.P.S., please use compressed file format, .jpg or png if you want to post graphics.
Frank
Super ContributorHello,
particularly the DCLK waveform doesn't look acceptable to me, the slow risetime is at risk to cause double clock edges at the receiver.
I guess you are performing PS configuration with open drain drivers, e.g. generated by a x51 processor. You should add pull-up resistors to the DCLK and DATA0 lines, or configure push-pull drivers if possible.
P.S., please use compressed file format, .jpg or png if you want to post graphics.
Frank
