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LakshmiPriya's avatar
LakshmiPriya
Icon for New Contributor rankNew Contributor
3 years ago
Solved

Intel Cyclone 10 LP FPGA DATA0 and DCLK waveforms

Hi, What is the expected waveform on DCLK and DATA0. I am seeing something as in the attached files. The waveform looks different for the first few cycles and changes in voltage levels after that. ...
  • FvM's avatar
    FvM
    3 years ago

    Hello,

    particularly the DCLK waveform doesn't look acceptable to me, the slow risetime is at risk to cause double clock edges at the receiver.

    I guess you are performing PS configuration with open drain drivers, e.g. generated by a x51 processor. You should add pull-up resistors to the DCLK and DATA0 lines, or configure push-pull drivers if possible.

    P.S., please use compressed file format, .jpg or png if you want to post graphics.

    Frank

FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
3 years ago

Hello,

particularly the DCLK waveform doesn't look acceptable to me, the slow risetime is at risk to cause double clock edges at the receiver.

I guess you are performing PS configuration with open drain drivers, e.g. generated by a x51 processor. You should add pull-up resistors to the DCLK and DATA0 lines, or configure push-pull drivers if possible.

P.S., please use compressed file format, .jpg or png if you want to post graphics.

Frank