Forum Discussion
KennyT_altera
Super Contributor
5 years agoYou may take a look in multicycle:
https://community.intel.com/t5/FPGA-Wiki/Timing-Constraints/ta-p/735562 ->
Understanding start/end setup/hold multicycle constraints
Or, this document: https://www.intel.com/content/dam/altera-www/global/en_US/uploads/3/3f/TimeQuest_User_Guide.pdf