Instantiating AHDL module in VHDL without component part

Hi,

I really like the idea of instantiating a module without a component part and then in main code using entity work. :

HA2 : entity work.halfadder port map (s1,cin,sum,c2);

The idea came from this link:

http://vhdlguru.blogspot.com/2010/03/entity-instantiation-easy-way-of-port.html

It works fine for my VHDL modules, but when i have some AHDL modules in my design and i want to instantiate them the same way, Quartus II gives me an error:

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Error (10481): VHDL Use Clause error at main.vhd(155): design library "work" does not contain primary unit "ahdl_module"

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Is there a way to work it around and not to use components when instantiating ahdl modules ? Perhaps quartus puts ahdl modules into some different library, or adds some name in the entity of that module - i wasn't able to find it.

best regards

madness