Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorInstantiating AHDL module in VHDL without component part
Hi, I really like the idea of instantiating a module without a component part and then in main code using entity work. : HA2 : entity work.halfadder port map (s1,cin,sum,c2); The idea came...
Altera_ForumHonored Contributor
Honored ContributorNope. For mixed language you need to use components, because the VHDL compiler has no knowledge of the AHDL, hence you need it to be a black box - which is what components are for.
