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Altera_Forum
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13 years ago

Instantiating AHDL module in VHDL without component part

Hi, I really like the idea of instantiating a module without a component part and then in main code using entity work. : HA2 : entity work.halfadder port map (s1,cin,sum,c2); The idea came...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Nope. For mixed language you need to use components, because the VHDL compiler has no knowledge of the AHDL, hence you need it to be a black box - which is what components are for.