Input signal from other board measures an extra cycle wider on signaltap on Stratix 10 vs Cyclone 5

Hi,

If that is the case, I think this also could be a signal integrity issue on the custom board, as the connection between the FTDI board and your Stratix 10 FPGA involves an adapter board and connectors, which likely introduces longer trace lengths compared to the direct on-board connection of the Cyclone V evaluation kit.

Different signals might experience different delays, potentially causing the RXF_N signal to arrive at the FPGA slightly earlier relative to the data signals.

Maybe you can use static timing analysis tools in the Quartus Prime software to analyze the timing of the signals arriving at the Stratix 10 FPGA. Pay close attention to the delays introduced by the board routing and the adapter.

Another method is to use the direct probe by oscilloscope, but as you said, this is not possible for you.