Initialise content in external memory when simulating a qsys system

It depends on the DDR2 memory model.

Look at the code for the memory component and see if it has initialization generics.

Look at the code and see how the memory array is implemented. If its implemented as a shared variable, you can use VHDL-2008 hierarchical access to initialize the variable.

If you have a mixed-mode simulator, and use a Verilog memory model, then you can use $readmemh to load the memory.

These various options depend on the memory model. I don't recall what Altera uses. I'd recommend creating a Qsys system with a DDR2 controller and then generating the example design. I've used this method to get the instantiation template for the memory model, and then copied that code into my own testbench.

Try some of these ideas, and if you get stuck, let me know and I can try looking to see what I have used in the past.

Cheers,

Dave