Initial value setting errir

I agree with @sstrell

For reference, here is what I see running your code ...

module test;

    initial
	begin
	$timeformat(-9, 0, "ns", 12);
	$dumpfile("test.vcd");
	$dumpvars(2,test);
	end

    reg start = 0;
    reg	stop = 0;
    wire state;

    initial
	begin
	#1000 start = 1;
	#100  start = 0;
	#300  stop = 1;
	#100  stop = 0;
	#500  $write("\n");
	$finish;
	end

    always @(start or stop or state)
	begin
	$write("%t start=%b stop=%b state=%b\n", $time, start, stop, state);
	end

    state u1 (start, stop, state);

endmodule // test

module state (start,stop,state);
    input start, stop;
    output reg state;

    initial state = 1'b0;

    always@(posedge start or posedge stop)begin
    if(start == 1) state = 1;
    else if(stop == 1) state = 0;
    else state = state;
    end

endmodule

and the result ...

GPLCVER_2.12a of 05/16/07 (Cygwin32).
Copyright (c) 1991-2007 Pragmatic C Software Corp.
  All Rights reserved.  Licensed under the GNU General Public License (GPL).
  See the 'COPYING' file for details.  NO WARRANTY provided.
Today is Wed Oct 12 11:17:09 2022.
Compiling source file "./test.v"
Highest level modules:
test

         0ns start=0 stop=0 state=0
      1000ns start=1 stop=0 state=0
      1000ns start=1 stop=0 state=1
      1100ns start=0 stop=0 state=1
      1400ns start=0 stop=1 state=1
      1400ns start=0 stop=1 state=0
      1500ns start=0 stop=0 state=0

Halted at location **./test.v(24) time 2000 from call to $finish.