Forum Discussion
Er7Cho1gU
New Contributor
3 years agoInitial value setting errir
Hello:
I'm new in verilog. Hopping that it's not a very stupid problem.
I'm tring to buid a FSM system using register "state" to perform the state now. There is no error hint or any fun...
sstrell
Super Contributor
3 years agoYour waveform does not show what you are saying in your post. I just see state as unknown or don't care throughout the sim.
If you are really trying to build an FSM, this is not the way to do it. You need two processes: one that is usually a clocked process (you have no clock here) that handles state transitions, usually based on input signals or the current state and one process that handles what the outputs should be when in a particular state. It's unclear what you're trying to do here.