Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Initial DFF values after FPGA programming

Normally I design my all my logic with an asynchronous reset, so this is not an issue, but I have recently come across an area where we might reload the FPGA via nCONFIG to reset it, and not have Use...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

--- Quote Start ---

A counter counting from reset state 0000 to next state 0001 in contrast can keep the reset state at worse.

--- Quote End ---

I was going to say the same.

But I wonder just out of curiosity, and would like yours and other experts opinion, if this is really 100% foolproof. Isn't it possible that the async reset release could produce setup/hold violations on the register output? If this is possible, then the next register in the counter could, in theory, become metastable.