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Power-up state can be considered reliable, the problem is with asynchronous release of power-up reset. As a consequence, a counter or state-machine can advance to an unexpected next state on a clock edge that coincides with reset release in some cases. But it can't advance to any arbitrary state, because each single register bit either keeps the reset state or takes the next state.
E.g. a one state hot state variable, advancing regularly from 1000 to 0100 can wrongly take 0000 or 1100, but no other state. A counter counting from reset state 0000 to next state 0001 in contrast can keep the reset state at worse. This is the reason, why the said reset controller counter always works reliably in my opinion. So if you want to provide an synchronous released reset but don't have an external reset signal, it's a good way.
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I'll try to find the thread about the reliability of power-up values that vjAlter mentioned and read up on it more. Since the power-up state is only unreliable in the sense that the reset/preset may act as being asserted at two different clock cycles for two different registers(this is even less likely if the registers are in the same LAB), a counter or shifter should work just fine. I'll consider this good design practice in the case where an external reset is not available.
Thanks for everyone's help.
Honored Contributor
