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Honored Contributor
Honored Contributorinference of multipliers from VHDL
Hello, I am working with a Cyclone 2, she has many 8*8 multipliers. I have a module where I use multiplications. After compiling my VHDL code I can see with the "RTL Viewer" the multi...
Altera_ForumHonored Contributor
Honored ContributorI'm not sure about the criteria that rule multiplier inference. But as long as the timing constraints are kept, there's no problem in using logic style multiplier, particulary with small word width. I hope, that Quartus changes to dsp style, if timing closure can't be achieved.
