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Honored Contributor
Honored Contributorinference of multipliers from VHDL
Hello, I am working with a Cyclone 2, she has many 8*8 multipliers. I have a module where I use multiplications. After compiling my VHDL code I can see with the "RTL Viewer" the multi...
Altera_ForumHonored Contributor
Honored ContributorYou may want to override the default behaviour by VHDL attributes, e.g. on an architecture level:
architecture rtl of my_design is
attribute multstyle : string;
attribute multstyle of rtl : architecture is "dsp";
