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If your oversampling frequency is high (i.e. at least 1 order of magnitude higher than the sampled signal) and decimation rate low (i.e. low number of added resolution bits), you can use a simple adder to solve the problem. Example: 8bit ADC, want 10bit ADC (2 bits added resolution) -> you need to add each 2^2=4 samples and use the result as your 10bit output. For 12bit output, you would have to add batches of 2^4=16 samples, and so on.
For lower oversampling frequencies you will have to use a weighted adder instead (do a search for 'exponential average' if you don't know what is that).
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All of this is in fact included if you design using the Altera FIR megawizard. It does the tedious work of construction of the adder network,
and puts weights on the taps
and calculates the frequency response as well!. The "exponential averager", "weighted averager", "running averager" etc. are simply FIR filters with specific tap values. In FIR compiler you can load tap-values (coefficient values ) from a simple text file if you are not content with the automatically generated values.
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Getting your hands dirty with DSP stuff is fun
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Yes, and the right tool makes it even more fun!
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