Forum Discussion
MaksimK30
New Contributor
New ContributorIncorrect PLL simulation in Questasim
Hello, everybody ! I'm new in FPGA and i have a problem with PLL simulation in Questasim. I'm create clear project, in Platform Designer add ALTPLL core and connect to clock source clk and reset. c...
Ok, I find my mistake. I incorrect write my testbench module. I should init all registers and add areset and locked wire from PLL
MaksimK30New Contributor
New ContributorOk, I find my mistake. I incorrect write my testbench module. I should init all registers and add areset and locked wire from PLL
