Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

In-System Programming with Cyclone III

Hello,

I have a custom board that uses the Cyclone III (EP3C40 - 240 pin) FPGA. The board has two headers for connecting to the ByteBlaster II. One of the headers is used for JTAG configuration straight to the FPGA to program the logic. This one works fine. The other uses the Active Serial In-System Programming configuration with a flash device (I have EPCS16). I've been able to program the serial configuration device in Quartus II using AS mode on the 'Programmer' window. I was able to Program/Configure and Verify (two check boxes selected) which programs to completion (100%) in Quartus II. The problem I've come across is that this doesn't seem to program my logic into the FPGA..

The logic design in VHDL is just a serial in parallel out shift register... I just had something simple to start with to test the board basically. So I have tested this logic which appears to work fine under ideal environment (dummy data and low freq clock signal) whenever I program the FPGA on it's own using JTAG mode. When I try out the AS mode with the EPCS16 the logic does not seem to be programmed in the FPGA (as my output from the shift register is all 0's no matter what input is used).

Just curious if there are any good tips/other parts of the Quartus II software I should be aware of?? I've tried also setting the MSEL pins to: MSEL[2] = 0, MSEL[1] = 1, MSEL[0] = 0... for active serial mode. I've tried this after programming the EPCS16 device, disconnecting power and programming cable from the board and then resupplying power to the board in hopes that the FPGA will be configured directly from the configuration device. Also, I just read a ditty about SFL (Serial FlashLoader) in an370, I don't know if maybe I need to use this, but it looks like a lot of work to get Quartus II using the SFL files for a workaround.. I am using the free web version of Quartus II v.11 so I'd like to avoid having to buy into any megafunctions or purchase the full software suite just for configuration.

I've attached a snapshot of the In-System Programming electronic configuration that the board is using:

Ok any help is much appreciated!!

Thank you in advance!!

~doddy

12 Replies

Show More
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Depending on the location of the 10 pF capacitor, it may also worsen things. I agree with Dave that a source side series termination can clear most ringing edge problems.

    --- Quote Start ---

    So for the SFL configuration, is the setup primarily done in Quartus tool to generate a .sof file for programming, and the circuit is just configured as I would for AS mode? My board has two headers, one which is set up for AS mode with the configuration device, and another which is for JTAG mode. So programming indirect JTAG mode, I'd assume that I would still connect my blaster to the header for AS mode yes? And then do the appropriate set up for the .sof file? Or am I way off track?

    --- Quote End ---

    Indirect JTAG programming means everything is done through the JTAG interface, with the help of the FPGA-internal JTAG hub and some additional code in the FPGA. It means that the second (AS programming) connector can be omitted.

    If you don't want to include the SFL MegaFunction in your final design (it's only necessary when a new image should be programmed during regular design operation), you can load the default SFL factory image shipped with Quartus for each FPGA type.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    If the DCLK trace routes from the FPGA to the EPCS device, and from an Active Serial programming header to the EPCS, the FPGA will effectively be driving two transmission lines; the one to the EPCS and the one to the header. Reflections at the end of those traces will propagate back towards the source, eg., if the trace to the AS header is the longest, that reflection will travel back past the trace going to the EPCS and cause ringing and bumps in edges there, and will then continue back to the FPGA, where it will reflect again, and so on. The ringing you see on the edges is due to multiple reflections.

    This is why most designers drop using an AS header. It serves no real useful purpose. The SFL IP core can be used to program the EPCS via the FPGA. Eliminating the AS header allows a point-to-point trace be routed from the FPGA to the EPCS device, and a source termination to be placed on the DCLK driver at the FPGA.

    If this is your own custom board, and you do have a long AS trace, and you can get to it where it splits to drive the EPCS and AS header, you could always cut the path to the AS header. Alternatively, place some capacitance on the DCLK driver pin/BGA ball to slow the edge-rate of the clock. That causes the reflections to be buried in the slower edge-rate ... it may or may not cure your issue.

    Cheers,

    Dave