In-System Programming with Cyclone III

If the DCLK trace routes from the FPGA to the EPCS device, and from an Active Serial programming header to the EPCS, the FPGA will effectively be driving two transmission lines; the one to the EPCS and the one to the header. Reflections at the end of those traces will propagate back towards the source, eg., if the trace to the AS header is the longest, that reflection will travel back past the trace going to the EPCS and cause ringing and bumps in edges there, and will then continue back to the FPGA, where it will reflect again, and so on. The ringing you see on the edges is due to multiple reflections.

This is why most designers drop using an AS header. It serves no real useful purpose. The SFL IP core can be used to program the EPCS via the FPGA. Eliminating the AS header allows a point-to-point trace be routed from the FPGA to the EPCS device, and a source termination to be placed on the DCLK driver at the FPGA.

If this is your own custom board, and you do have a long AS trace, and you can get to it where it splits to drive the EPCS and AS header, you could always cut the path to the AS header. Alternatively, place some capacitance on the DCLK driver pin/BGA ball to slow the edge-rate of the clock. That causes the reflections to be buried in the slower edge-rate ... it may or may not cure your issue.

Cheers,

Dave