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Altera_Forum
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13 years ago

In-System Programming with Cyclone III

Hello, I have a custom board that uses the Cyclone III (EP3C40 - 240 pin) FPGA. The board has two headers for connecting to the ByteBlaster II. One of the headers is used for JTAG configuration...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

A simple test that should be always done is verifying the EPCS content in Quartus programmer. If it fails, there's most likely a problem with the programming interface, e.g. signal quality issues. Otherwise the EPCS to FPGA interface and related signals should be thoroughly checked. Also in this case, signal integrity might be the problem, e.g. double clocking due to ringing DCLK signal.

Not directly related to the problem, but I don't agree about difficult usage of indirect JTAG programming (SFL). I'm using it since many years for all designs with AS configuration scheme.