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I am sub-compiling and logic locking a module. The source files are all called using relative paths.
When I run the top level compile I get an error in the assembler stage indicating that it cannot find the relative paths of the sub-compiled module.
The build still runs and generates the correct rbf file, but the sof file is not generated.
Since the sub-compile and the top-level compile are in different folders, the sub-compile relative paths would not make sense in the top-level directory.
In the top-level .qsf I provided the relative paths to the sub-compile source files, but it still seems to be using relative paths from the sub-compiled build.
Hopefully this make sense .. anyone know how to get around this.
thanks
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Hi flipper,
I do not understand what you are trying to achieve. As far as I know you can't generated sof-files for the Toplevel and the Sublevel , combine them and programm the FPGA. I never heard of that.
Of course you can run the Subdesign in a separate project. You have to define a design partition and a LockLock region. After succesful P&R you have to export the design as design partition. In the Toplevel project you have to define your sublevel design also as design partition. I have a small example project attached.
Kind regards
GPK
Honored Contributor
