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Altera_Forum
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12 years ago

Implementing LVDS transmitter in altera EP4CGX15 - Basic information

Hello all - I am a beginner implementing LVDS transmitter on a EP4CGX15 device with 4 data pairs and 1 clock pair. The data sheet tells me that bank 5 and 6 can generate true LVDS without ...
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Altera_Forum
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12 years ago

1) Yes. The PLLCLKOUT function those pins offer is reserved for direct, low jitter output paths from the PLLs. You might (although I suspect you won't) be able to route the ALTLVDS_TX generated clock to the PLLCLKOUT pins only by virtue of the fact they are also general purpose I/O pins. However, they don't explicitly state those pins support differential I/O, except when used for their PLLCLKOUT function.

2) No, not really. Your chosen bank may or may not have dedicated CLKx pins. Feed the XO output clock into a CLKx pin in a bank powered at the appropriate voltage for the XO. Quartus will be able to use a CLKx signal throughout the device, not just in the bank it feeds.

Regards,

Alex