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Altera_Forum
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12 years ago

Implementing LVDS transmitter in altera EP4CGX15 - Basic information

Hello all - I am a beginner implementing LVDS transmitter on a EP4CGX15 device with 4 data pairs and 1 clock pair. The data sheet tells me that bank 5 and 6 can generate true LVDS without ...
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Altera_Forum
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12 years ago

Thanks a_x_h_75. That answers almost all of my questions.

1) If I configure ALTLVDS_TX to generate a clock from the same primitive then I should route the output clock to the available DIFFIO pins in that bank rather than the PLLCLKOUT pins. Is that right ?

2) The XO crystal feeding clock can be connected to the global CLKx input pins in the intended bank. Is that right ?

Appreciate your time.