Honored Contributor
Honored ContributorThe best way to answer some of your questions is to put together a sample project and run it through Quartus. Bank 6 looks like a good choice, allowing you to drive True LVDS.
1) Yes, ALTLVDS_TX is the primitive to use to drive LVDS signals from the FPGA. Providing you've chosen DIFFIO pins then you should be OK. However, if you're assigning any other single ended signals in the vicinity of these LVDS signals, Quartus may well complain about cross talk and not fit your design. 2) Yes, PLL_CLKOUT will drive a clock out of the FPGA. Those pins have the added advantage that the source of that clock can be from a PLL. (DIFFCLK pins are input only). 3) The ALTLVDS_TX primitive will generate a clock, synchronous to (and a frequency multiple of) the data generated from the same primitive, if you select that option when configuring it. You will be able to route this clock out of the device. 4) Yes you will need an external oscillator for the FPGA. It doesn't have an internal one (except for configuration and you can't use it). Put together a simple project instantiating the primitives discussed, run it through Quartus and it'll let you know whether it's happy or not.
