Honored ContributorHi everyone,
I'm new at the Altera Forum and I'm also a newbie in using Altera FPGAs. In order to design a packet filter for a DVB application, I'm looking for a solution to implement a CAM (Content Addressable Memory) on a Cyclone-III FPGA. Can anyone help me with that? Thanks in advance Modellpilot
Honored ContributorHi, I have a doubt abou this. This CAM size that a M9K block can implement is number of words X number of bits of each word or it is number of bit address X number of bits of each word?
Thanks in advance!!!:)Honored ContributorNeither, at least with the design I posted, it's a 32x8 CAM. Be sure to look at it, since is uses different widths between reads and writes. On the write side, the data AND address are combined into a single write address. This implementation allows the write and read to occur in a single clock cycle.
It seems like a huge reduction from all the bits in an M9K down to just a 32x8 CAM, but that's because it's just a RAM. A CAM needs to look at all locations for a match, so if you really wanted to store a word at each location, then you would need a state-machine that reads every location and checks for a match, i.e. it would be MANY clock cycles for each read. Some designs can tolerate this, but it quickly becomes unmanagable. The one I posted is very straightforward in implementation(once you understand how it works), but is small. I've seen plenty of cases where users need a much larger CAM and find they're dedicating all of the memory to this function and hence this implementation doesn't work.Honored ContributorThanks for the tips!! But I need a CAM with 64 words X 64 bits wide, what do you suggest for implement this kind of CAM?
Once more, thanks!!:)Honored ContributorThe HDL is parameterized, so just put that in. I believe a 64x64 will require 16 M9Ks(x2 to get the width and x8 to get the depth). That should be do-able.
Honored ContributorDo you have parameterized_cam in Verilog code?
Honored ContributorI have created a Verilog parameterized CAM that you may find useful. I'll attach it here. It is a Quartus II archive file that contains a simulation environment in the sim directory, and some documentation in the doc directory.
Honored ContributorDear Rysc,
Can your Parameterized_CAM be configured to parameter NUM_WORDS = 4096; parameter WRADDR_WIDTH = 12; parameter WIDTH = 16; or not ?Honored ContributorWhat happened when you tried it? If the base M9K makes a 32x8 CAM, then the depth and width look like multiples, so I see no problem. Although I think it's going to take 256 M9Ks to get that, so it will use a lot of resources.
Honored ContributorWith FOR loop times from 2048 to 4096, the PC can not synthesize, out of memory in module quartus_map.exe
May be the numbers of loop is too larger to synthesize
Honored ContributorHi,
I am new to this and I have a query. Is this code valid for cyclone 4 too? I am not having altsyncram option in here. I have a M9k block and need a CAM of 128 bytes memory with 8 bits of data and 8 bits of address. Thanks --- Quote Start --- An M9K can do a 32x8 CAM, so you'll basically change the parameters in M9K_CAM.vhd to do a 32x16 CAM(it needs to be a multiple of these dimensions), and then just tie off the extra ports. I built this quickly but believe it is correct. There is a presentation that is very old on this topic(it was done as Stratix was rolling out). I have a document that refers to it, so together you can use them for understanding. (Not the most professional delivery, but hey, if it works.) You can also just use the M9K_CAM.vhd and M9K.vhd files and just play with it yourself. --- Quote End ---
