Implementing CAM (Content Addressable Memory) on Cyclone III

Neither, at least with the design I posted, it's a 32x8 CAM. Be sure to look at it, since is uses different widths between reads and writes. On the write side, the data AND address are combined into a single write address. This implementation allows the write and read to occur in a single clock cycle.

It seems like a huge reduction from all the bits in an M9K down to just a 32x8 CAM, but that's because it's just a RAM. A CAM needs to look at all locations for a match, so if you really wanted to store a word at each location, then you would need a state-machine that reads every location and checks for a match, i.e. it would be MANY clock cycles for each read. Some designs can tolerate this, but it quickly becomes unmanagable. The one I posted is very straightforward in implementation(once you understand how it works), but is small. I've seen plenty of cases where users need a much larger CAM and find they're dedicating all of the memory to this function and hence this implementation doesn't work.