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Preferably we would use the word clock (25 MHz) to synchronize the deserializer. A 450 MHz clock would be above acceptable Cyclone clock tree frequencies. The LVDS receiver uses 225 MHz and DDIO registers internally.
The 25 MHz word clock must be nevertheless transmitted with low jitter, so you should use differential pairs and dedicated LVDS receivers for clock and data lines.
Synchronizing on start bit isn't a standard feature of the deserializer block but basically possible by additional logic.
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Hmm, that introduces another challenge. I would have to convert the sensor clock to LVDS. That's probably possible through some converter. I will look into that.
Do you know which part is the most low cost part that will accept an LVDS clock of 450Mhz? This is probably already high end, right?
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