Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Implementing 18-bit lvds serializer in CPLD

Hello, Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Preferably we would use the word clock (25 MHz) to synchronize the deserializer. A 450 MHz clock would be above acceptable Cyclone clock tree frequencies. The LVDS receiver uses 225 MHz and DDIO registers internally.

The 25 MHz word clock must be nevertheless transmitted with low jitter, so you should use differential pairs and dedicated LVDS receivers for clock and data lines.

Synchronizing on start bit isn't a standard feature of the deserializer block but basically possible by additional logic.