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Honored Contributor
Honored ContributorImplementing 18-bit lvds serializer in CPLD
Hello, Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-...
Altera_ForumHonored Contributor
Honored Contributor450 MHz is feasible as Cyclone LVDS clock rate, but it's a bit high for "software" clock recovery. It might work, but I didn't yet implement CDR at higher bit rates than 240 MHz. The standard configuration, fully supported by Quartus IP would feed the word clock to the Cyclone PLL and generate the fast clock by frequency multiplying, without clock recovery. I don't know if transmitting the word clock is feasible for your application?
