Implementing 18-bit lvds serializer in CPLD

What's the intended bit rate? Low cost FPGA (Cyclone series) neither have a decicated clock recovery hardware, but CDR can be implemented for medium bit rates utilizing PLL dynamic phase shift or oversampling with multiphase clocks.

MAX II/V is the only Flash FPGA available from Altera. It's named CPLD according to the low logic element count , but actually using SRAM FPGA technology.

P.S: I assume the bit rate is 450 MHz, 18*25 MHz?