Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorImplementing 18-bit lvds serializer in CPLD
Hello, Maybe this is a beginners question. I do not yet have a lot of experience using CPLDs. They are a bit more limited than FPGAs. I was wondering if it is feasible to implement an 18-...
Altera_ForumHonored Contributor
Honored ContributorWhat's the intended bit rate? Low cost FPGA (Cyclone series) neither have a decicated clock recovery hardware, but CDR can be implemented for medium bit rates utilizing PLL dynamic phase shift or oversampling with multiphase clocks.
MAX II/V is the only Flash FPGA available from Altera. It's named CPLD according to the low logic element count , but actually using SRAM FPGA technology. P.S: I assume the bit rate is 450 MHz, 18*25 MHz?
