New ContributorImplementation of a custom streaming sink for the Modular ADC Core on a MAX10M08 Ev Kit not working. Any idea why?
I'm trying to implement a custom IP as a streaming sink for the modular ADC core, showing the actaul converted data on the LEDs of the MAX10M08 Ev Kit.
Somehow I am unable read out the data in the custom IP core. With the ADC Toolkit I am able to check, that the ADC is up and running. With the RTL Viewer I am able to see, that the ADC core is wired correctly togther. But I'm not able to display any data, no matter whatever I'm trying.
Does anybody has a some advice/hint?
Below you'll find the code of my custom IP:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY led_st_sink IS
PORT(
csi_clk : IN std_logic;
rsi_reset_n : IN std_logic;
avm_csr_address : OUT std_logic_vector(2 downto 0);
avm_csr_read : OUT std_logic;
avm_csr_write : OUT std_logic;
avm_csr_writedata : OUT std_logic_vector(31 downto 0);
avm_csr_readdata : IN std_logic_vector(31 downto 0);
avm_csr_waitrequest : IN std_logic;
asi_adc_valid : IN std_logic;
asi_adc_channel : IN std_logic_vector(4 downto 0);
asi_adc_data : IN std_logic_vector(11 downto 0);
asi_adc_startofpacket : IN std_logic;
asi_adc_endofpacket : IN std_logic;
coe_led : OUT std_logic_vector(4 downto 0)
);
END led_st_sink;
ARCHITECTURE rtl of led_st_sink IS
SIGNAL adc_run : std_logic;
BEGIN
adc_start : PROCESS(csi_clk, rsi_reset_n)
BEGIN
IF rsi_reset_n = '0' THEN
adc_run <= '0';
avm_csr_address <= "000";
avm_csr_read <= '0';
avm_csr_write <= '0';
avm_csr_writedata <= x"00000000";
ELSIF rising_edge(csi_clk) THEN
IF adc_run = '0' THEN
avm_csr_write <= '1';
avm_csr_writedata <= x"00000001";
ELSE
avm_csr_write <= '0';
avm_csr_writedata <= x"00000000";
END IF;
END IF;
END PROCESS adc_start;
adc_st_read : PROCESS(csi_clk, rsi_reset_n)
BEGIN
IF rsi_reset_n = '0' THEN
coe_led <= "00000";
ELSIF rising_edge(csi_clk) THEN
IF asi_adc_valid = '1' THEN
coe_led <= asi_adc_data(11 downto 7);
END IF;
END IF;
END PROCESS adc_st_read;
END ARCHITECTURE rtl;
