Implementation of a custom streaming sink for the Modular ADC Core on a MAX10M08 Ev Kit not working. Any idea why?

Your code has some flaws.. for starters, the signal adc_run is assigned '0' in the first process on the assertion of reset, but after this in the clock loop, is checked if it is '0' and not assigned any other value. This will infer latches for this signal. Plus, the signal will always be assigned to '0' and will never change, making the else part of the code unreachable. You should assign the signal in the process and use it in the another process to prevent latch inference.

The same goes for the avm_csr_read and avm_csr_address signals. Correct the code, run a functional simulation, and also check the synthesis report after compilation.