Forum Discussion
Hello JwChin and Abe
Thanks for your hints. Adapting my code accordingly the Odyssey example showed first positive results (response streaming sink and sequencer MM master in the top entity, only PLL and ADC in the QSYS). From there on I continued my investigations.
I've figured out, that my streaming sink did not fully match the streaming source of the ADC IP, and therefore QSYS added an auto-inserted ST adapter. This adapter did not pass through the valid signal. After completely matching all signals, witdh, bits per symbol, max. nr. of channels, ... QSYS did not add any adapter anymore and everthing startet to work as it should.
Concerning the flaws in my code: They will of course be all corrected as soon as I'm starting to implement the real intended function of my custom IP. First goal is now reached, the ADC core is successfully connected.